AMD’s upcoming Ryzen desktop processors, reportedly codenamed “Olympic Ridge,” are expected to introduce a significant architectural change. These processors are anticipated to utilize the Zen 6 core design to boost desktop core counts. By adopting TSMC’s N2 2nm manufacturing process, AMD has reportedly achieved the transistor density necessary to integrate up to 12 cores per CCD, a notable increase compared to the 8-core limit of previous Zen 4 and Zen 5 generations.
This architectural advancement, as detailed in HXL’s recent report on future AMD Ryzen CPUs (via VideoCardz), is expected to facilitate a broader range of product offerings. Single-CCD configurations are projected to include CPUs with 6, 8, 10, and 12 cores, while dual-CCD processors could feature 16, 20, and 24 cores.
The transition to the 2nm manufacturing node not only enhances core density but also creates additional room for on-die resources. Each Zen 6 core is anticipated to incorporate 4 MB of L3 cache, leading to 48 MB per CCD and a combined 96 MB for dual-CCD models. This fundamental cache enhancement is planned for release on the current AM5 socket, aligning with AMD’s commitment to extended platform support until at least 2027.
3D V-Cache variants are expected to be introduced several months after the initial Zen 6 desktop lineup. These specialized AMD CPUs could potentially offer up to 288 MB of L3 cache, assuming a limit of 96 MB of 3D V-Cache per CCD, within the coming year.
